A primary factor in the utility of a computer system is its speed in executing application programs. A high-performance computer system is expected to be responsive to user inputs and to accurately provide processed results within real-time constraints. A primary factor in the speed and responsiveness of a computer system is the efficiency of its processor subsystem, memory subsystem, IO (input output) subsystem, and the like. Large investments have been made in the development of very high-speed processors and high-speed memory subsystems. Consequently, the computer industry has seen remarkable annual improvements in computer system performance. A comparatively new area of focus for improving computer system performance is the input output mechanisms involved in accessing and storing data.
Data is typically stored on attached hard disk drives. Disk drives having size of 200 GB or more are increasingly common in desktop and laptop computer systems. Fast and efficient access to data stored on such drives is important to responsiveness and functionality of typical user applications.
ATA (AT Attachment) is a widely supported specification that defines methods of accessing data on disks. The ATA specification evolved from the earlier IDE (integrated drive electronics) specification. ATA defines a type of hardware interface that is widely used to connect data storage peripheral devices such as hard disk drives, CD-ROMs, tape drives, and the like, to a computer system. The ATA standard has further evolved to accommodate additional device types and data transfer features. For example, ATAPI (ATA Packet Interface) defines a version of the ATA standard for CD-ROMs and tape drives, ATA-2 (Fast ATA) defines the faster transfer rates used in Enhanced IDE (EIDE), and ATA-3 adds interface improvements, including the ability to report potential problems.
ATA devices have shown dramatic increases in data transfer speed and storage capacity over time. However, computer systems using such faster devices have not fully shown the expected performance improvements. A number of interface problems with computer system I/O components are partially responsible for the performance limitations, such as, for example, the data transfer characteristics of the PCI bus (e.g., due to the need to retain host adapter PCI compatibility), the interrupt based data transfer mechanisms, and the like.
The ADMA (Automatic DMA) specification comprises a new specification designed to improve the performance of ATA type devices. ADMA is designed to add features that improve the data transfer speed and efficiency of ATA devices. For example, ADMA adds support for multi-threading applications, command chaining techniques, command queuing, and the like, which are intended to have the overall effect of decoupling the host command sequence from the channel execution. The objective of the ADMA standard is to dramatically increase the performance of computer systems that operate with ATA type devices.
Problems exist, however, with respect to how ADMA implements disk transactions with a disk controller. As described above, one objective of ADMA is to improve the data transfer speed and efficiency of ATA devices. Accordingly, the ADMA specification defined an improved method of implementing read transactions and write transactions with an ATA hard disk, in comparison to the conventional ATA defined transactions. For example, conventional ATA defined a disk I/O requiring a series of write transactions to a set of 8-bit registers within a disk controller. In the earlier ATA specification, read/write transactions required a series of 8-bit reads/writes to these IO mapped registers, causing the computer system to incur a significant latency and overhead burden.
The ADMA specification included a number of improvements over the earlier ATA disk transactions. One improvement involved the use of system memory to build a disk transaction as opposed to the set of 8-bit registers in the disk controller. Another improvement involved the use of a DMA transfer from the system memory to the disk controller to implement the disk transaction. For example, ADMA defined disk transactions as beginning with the preparation of a disk transaction by the processor (e.g., a driver executing on the CPU). This preparation includes generating and arranging the transaction information, including the PRDs (physical region descriptors) and CPBs (command parameter blocks) for the transaction. The transaction information is then loaded into system memory (e.g., at a particular address). The processor then pushes a pointer to the system memory location (e.g., for the disk transaction information) to the disk controller. The disk controller then uses the pointer to access system memory and retrieve the disk transaction information. Once the disk controller has the necessary transaction information, the disk controller issues commands to start up the disk drive mechanism and implement the disk transaction.
Problems remain, however, with respect to excessive amounts of latency and overhead within the ADMA disk transaction methodology. For example, one problem is due to the fact that the transfer of transaction information from the processor to system memory and then to the disk controller involves a number of arbitration and transfer operations on the buses linking the processor, system memory, and disk controller. These bus transactions can each incur two to four microseconds of latency. Another problem is due to the fact that the disk controller does not start the disk drive mechanism to begin transaction until it has received the transaction information (e.g. via DMA transfer) from system memory. Thus, the overall transaction must suffer through the latency involved in the start up of the disk drive mechanism, which can be another two to four microseconds.
The latency and excessive overhead problems of ADMA disk transaction methodology can significantly detract from overall computer system performance. As processor and system memory performance continue to show annual improvement, it becomes increasingly important that disk I/O systems show similar improvements. As latency penalties are reduced in other components of a computer system (e.g., data transfer buses, graphics operations, etc.) it becomes increasingly important that the disk I/O system shows similar degrees of improvement with respect to reduced latency, overhead, and the like, in order to avoid imposing performance bottlenecks on the overall computer system.